GLOBAL FOUNDARIES is hiring as Intern- VLSI Design Engineer


Company Name : GLOBAL FOUNDARIES

Company website- Open Site

Position for Applying:  Intern- VLSI Design Engineer

Education Required - Post graduate/Masters - ME/MTech/MS

Experience - 0-1 year

Passed outs - 2019/2020/2021

Location: Remote


About the Role -

Obligations might be very assorted of a specialized sort. Experience and schooling necessities will fluctuate altogether relying upon the remarkable requirements of the work. Occupation tasks are generally for the mid year or for brief periods during parts from school for least of a half year and max 11 months . 


Your duties will incorporate a portion of the accompanying however not restricted to:- Assist plan unit proprietor in Register Transfer Level (RTL) demonstrating and useful approval. Use EDA instruments widely to reproduce rationale conduct and circuit execution and course of actual plan for future, profound sub-micron implanted circuit arrangements. Confirm the circuit conduct against the first recreation model and first silicon.- Define VLSI Structural Design strategy and creating configuration streams. Carry out primary actual plans, like amalgamation, floor arranging, power-network and clock tree plans, timing planning and conclusion, spot and course, RC-extraction and combination. Confirm underlying actual plans, like useful equivalency, timing/execution, commotion, format configuration rules, unwavering quality and force.- Develop Analog IP on cutting edge profound submicron measure for the Global foundries client SOCs, perform undertakings identified with Very-enormous scope reconciliation (VLSI) corresponding metal-oxide-semiconductor (CMOS) IC plan and FINFET based plans, Solid state physical science and actual design. Such assignments may include: Circuit plan of fast timing related circuits [phase-bolted circle (PLL), delay-bolted circle (DLL), bandgap] or high voltage input/yield (IO) , General-reason input/yield (GPIO), OPIO].- Responsible for Integration of Third gathering IPs - Synthesis, useful and additionally timing intermingling, and pre and post-si troubleshoot of IPs created by different outer merchants just as inside the Global foundries . Treatment of signs crossing power planes and clock spaces, industry standard conventions including equipment and programming subtleties managing Embedded Memories . Framework incorporation managing Si/Platform/FW/MW/drivers/OS/Apps on Android and Windows-based frameworks .


Qualification -

  1. good understanding of semiconductor physics and basic PC computer architecture
  2. Familiarity with Very Large Scale Integration (VLSI) Complementary Metal-Oxide Semiconductor (CMOSand Finfet ) logic circuit design
  3. Well versed in UNIX*, C programming and relevant Computer Aided Design (CAD) tools 


Apply Link - Click here


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